During front end-of-the-line processing, a plurality of semiconductor devices (e.g., transistors, resistors, capacitors, and the like) are formed on a semiconductor wafer. During Back End-of-the-Line (“BEoL”) processing, the semiconductor devices are interconnected to form a plurality of integrated circuits on the wafer, which are subsequently separated into individual die during wafer dicing. Interconnection of the semiconductor devices is accomplished via the formation of electrically-conductive features (e.g., interconnect lines and conductive contacts or plugs) in a plurality of dielectric layers successively deposited over the semiconductor devices during BEoL processing. For example, contact openings are etched in the first dielectric layer deposited directly over the semiconductor devices (commonly referred to as the “pre-metal dielectric layer”), a conductive material (e.g., tungsten) is deposited into the contact openings, and the excess conductive material is removed by chemical mechanical planarization to produce a plurality of conductive contacts or plugs embedded in the pre-metal dielectric layer and in ohmic contact with electrically-active elements of the semiconductor devices (e.g., doped regions, gate electrodes, etc.). Similarly, during fabrication of the BEoL metal levels, contact openings and trenches are etched within each inter-level dielectric (“ILD”) layer and a sacrificial capping layer formed over each ILD layer, filled with copper (or other conductive material), and the excess copper is removed to yield a plurality of conductive interconnect features (contacts and interconnect lines) electrically interconnecting the semiconductor devices of the integrated circuits.
After metallization of each BEoL metal level, a chemical mechanical planarization (“CMP”) polish process is commonly performed to remove the excess copper from over the newly-patterned ILD layer. The CMP polish process is often performed in multiple successive stages concluding with a barrier polish stage wherein the sacrificial capping layer is removed, along with an upper portion of the ILD layer and the interconnect features, to impart the ILD layer with a substantially planar upper surface. As conventionally performed, the barrier polish is carried-out for a fixed duration of time sufficient to ensure complete removal of the capping layer. However, while polish duration can be held consistent through repeated iterations of the barrier polish, the rate of material removal generally cannot due to unavoidable discrepancies in the chemical behavior of polish consumables and in the performance of the CMP tooling (e.g., variation in polish pad removal rates). Consequently, the thickness removed from the ILD layer and from the interconnect features, and thus the post-CMP thickness of the ILD layer and interconnect features, can vary significantly between iterations of the barrier polish process. Such variations in the post-CMP thickness of the ILD layer and interconnect features result in correspondingly large variations in metallization layer resistance, which is especially problematic in smaller devices (e.g., circuit designs for semiconductor generations equal to or less than 32 nanometers), and an undesirable reduction in overall wafer-to-wafer, lot-to-lot, and wafer-in-wafer uniformity.
It would thus be desirable to provide embodiments of an integrated circuit fabrication method wherein inter-level dielectric and interconnect feature thicknesses are consistently maintained within relatively narrow ranges through successive iterations of the post-metallization polishing process to improve wafer-to-wafer, lot-to-lot, and wafer-in-wafer uniformity. It would also be desirable to provide embodiments of an integrated circuit produced in accordance with such a fabrication method. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Technical Field and Background.